The present invention relates generally to semiconductor integrated circuits, and, more particularly, to a method and apparatus for reducing void formation induced failures caused as a result of stress-migration characteristics of conductors in integrated circuits.
Since the introduction of integrated circuit (IC) devices, there has been a continuous drive to improve their quality, reliability and cost/unit. This drive has been fueled by consumer demand for improved computers and electronic devices, which are more reliable, cost less, occupy less space and use less power.
In a semiconductor fabrication process, IC's are fabricated by sequentially forming features in layers of material in a bottom-up manufacturing method. The manufacturing process utilizes a wide variety of processing and measuring tools and techniques to form various layered features.
Reliability is a significant factor in IC design, production and operation. Process parameters are tightly controlled to ensure high reliability during all stages of manufacturing process. Where feasible, samples are taken and tests are performed at many intermediate stages of the process so corrective action may be taken if found to be necessary. The importance of precise control of process parameters such as thickness, dopant concentration, gate length and temperatures will be appreciated when it is realized that IC manufacturing typically requires precise execution of hundreds of steps. Completion of all steps for each wafer may typically require several days or even weeks. An improvement in the reliability of the circuit design itself and in the manufacturing process is important to avoid a significant economic loss of wafers themselves and in lost opportunity to meet customer demand. Various factors affecting reliability of a semiconductor device are described in FIGS. 1A through 1D below.
FIGS. 1A, 1B, 1C and 1D are illustrative diagrams of interconnect structure between two adjacent layers of interconnection in a state-of-art IC with multiple layers of interconnection not shown) according to prior art. FIGS. 1A and 1C are views in perspective illustrating the interconnect structure and FIGS. 1B and 1D are cross sectional views of the interconnect structure. Referring to FIGS. 1A and 1B, conductors 110, 115, and 120 are connected through vias 130 and 140 or through holes. The lower metal line 115 is narrower compared to the other metal lines 110 and 120. Hence, if there is a current flowing from metal 120 through via 140, metal line 115, via 130, and metal 110 as shown in FIG. 1A with the electron current flowing in the opposite direction of current flow, the narrower metal line 115 carries a higher current density than metal lines 110 and 120. A low k dielectric 190 is used as insulator. Similarly, in FIGS. 1C and 1D, conductors 110, 117, and 120 are connected through vias 130 and 140. The upper metal line 117 is narrower compared to the other metal lines 110 and 120. The low k dielectric 190 is used as insulator. The conducting materials of metal lines and vias typically used in CMOS technology include aluminum, aluminum alloys, refractory metal, copper, copper alloys, gold, gold alloys, silver, silver alloys, and the like, and doped polysilicon and silicides.
Typical examples of various components interconnected by metal lines and vias within an IC include transistors, diodes, resistors, capacitors, contact terminals and the like. Advances in sub-micron CMOS technology generally requires that the interconnect density be enhanced by decreasing the metal pitch and via size as well as increasing the number of interconnect metal layers. Therefore, as the dimensions of the active devices decreases and interconnect density increases, there is typically higher current density flowing in metal lines and vias. The increased time constant and reduced reliability of multi-level interconnection are considered major possible limitations to the circuit performance.
One factor affecting reliability of IC is the mechanical stress migration of metal lines and vias. As is well known, the mechanical stress migration is the movement of atoms of the conducting material from which the conductor is fabricated as a result of residual stress caused by the mismatch of thermal expansion coefficients between the metal and surrounding dielectric materials. The residual stress is typically tensile as the thermal expansion coefficients of usual conduction materials are typically larger than that of the surrounding insulator. The magnitude of tensile stress in metal lines is bi-axial and larger with wider dimension. Further, the mechanical stress migration occurs most significantly at elevated temperatures (e.g. ˜100-200° C.). At such temperature range, the atomic movement in metal line is more significant due to atoms energetic enough under large enough mechanical stress. There is no significant atomic movement either at too high a temperature e.g. >300° C. (due to much reduced residual mechanical stress in metal line) or at room temperature due to not enough energy of atoms.
Another factor affecting reliability of IC is the electro-migration, which is known as the migration of metal atoms e.g. copper atoms in a conductor along the direction of electron flow (or to the opposite direction of electrical current flow as defined conventionally. The migration of metal atoms will occur more significantly on locations where there is larger electron current density e.g. locations of metal line near corners, inside vias near bottom and locations at elevated temperatures e.g. due to local excessive thermal generation by current paths. Both the mechanical stress migration and electro-migration results in damage in terms of void formations and formation of hillock growths or accumulations that enlarge over time. These voids will eventually leads to circuit failures by open or high resistive metal lines or vias. These hillocks will eventually leads to circuit failures by shorts or lower breakdown voltage in between metal layers. Even when there are no substantial mechanical stresses present, electro-migration may still occur provided there is a large enough current density flowing at high enough operating temperature e.g. 80-150° C. Similarly, even when there is no current flow, mechanical stress migration can also occur provided there is large enough mechanical stress at high enough operation temperature. Thus, the mechanical stress migration and electro-migration are two independent failure mechanisms of multi-level inter-connection in modern VLSI; however, these two mechanisms may work collectively together for accelerating void formation, or they may influence each other for suppressing the net atomic migration depending on the electron flow direction. Some techniques for minimizing mechanical stress migration may also reduce electro-migration and improve reliability of multi-level inter-connection in VLSI.
Referring to FIG. 1B, voids or void formation 160 may be formed adjacent to via bottom below the barrier metal of via on the cathode side 132 e.g., via 130 bottom by electro-migration of copper atoms along electron flow 150, and copper accumulation occurs at the anode side 142 e.g., via 140. The mechanism of void formation by electro-migration is thus related to the movement of copper atoms away from the via bottom 132 along the direction of electron flow 150 or alternatively copper vacancies moving towards the via bottom along the direction of current flow.
As described earlier, voids may also be formed due to mechanical stress migration, when there is no current flowing through metal lines and vias (i.e. there is no electro-migration in this case). In a via structure with wide upper metal, similar to FIG. 1B, void may be formed above the barrier metal near via 130 or 140 bottom not shown in FIG. 1B as a result of larger tensile stress in the wider metal lines 110 and 120 than the stress in narrower metal line 115 and the inside of vias 130 and 140. Thus, there is a net mechanical stress encouraging Cu atoms movement toward the upper wide metal line 110 and 120 with void formed above the via bottom. Note that the barrier metal between the metal line 115 and the bottom of via 130, 140 prevents those Cu atoms moving toward the upper wide metal line 110 through the barrier from the narrow metal line 115; as a result, the void by mechanical stress migration in this structure is typically formed above the barrier near via bottom. Certainly, as described earlier, both mechanical stress migration as well as electro-migration can result in formation of voids in a collective manner.
Now referring to FIG. 1D, the narrower upper metal line 117 carries higher current density than the wider metal line 110, 120 and it is similar to metal line 115. Voids 160 are formed in via 130 bottom above the barrier metal and copper line corner at cathode side 132 along the direction of electron flow by electro-migration mechanism. In the via structure with wide lower metal, similar to FIG. 1B, stress induced voids may be formed below barrier metal near via 130 as a result of mechanical stress migration by the larger magnitude of tensile stress in wider metal line 110 or 120.
As described earlier, void formation, such as the formation of void 160, is generally associated with tensile stresses in metal line. However, those atoms moving from voids will finally accumulate elsewhere nearby and form hillocks. The local area near hillocks in metal line generally has less tensile stress or even compressive stresses. The void formations result in an increased resistance and may eventually cause an open circuit failure in the interconnect. The accumulation (or hillocks) results in fracturing the surrounding passivation layers and may produce short circuits between neighboring interconnects. Obviously, both void formation and accumulation negatively impacts chip reliability.
The IC interconnects have been traditionally made from aluminum and its alloys. However, in recent years, the use of copper and copper alloys in combination with materials of lower dielectric constant as insulators has increased due to lower resistance (compared to aluminum) and reduced capacitance values for the interconnects. However, because copper is not easily etched it requires new processing methods, notably the damascene process with chemical-mechanical polishing (CMP).
The following technical publications describe various aspects of reducing mechanical stress induced voiding [1-3] and electro-migration induced voiding [4-5] in copper interconnects to improve reliability and are incorporated herein by reference:
a. K. Y. Y. Doong, and et al., stress induced voiding and its geometry dependency characterization. IEEE international Reliability Physics Symposium, p. 138, 2003.
b. I. Oshima, et al., Suppression of stress-induce voiding in Copper interconnects, Technical Digest of IEDM, p. 757, 2003.
c. E. I. Ogawa, et al., Stress induced voiding under vias connected to wide Cu metal leads. IEEE international Reliability Physics Symposium, p. 312-321, 2002.
Presently, traditional techniques to reduce mechanical stress migration rely on adding extra process steps in the fabrication process. For example, those well-known techniques for reducing void formation include improving via shape, via cleaning, barrier metal adhesion improvement, increasing copper grain size by annealing, and implementing dual vias to wide metal lines. However, virtually all of these techniques also require adding extra steps to the manufacturing process, thereby adding extra costs, complexity and time delays.
Thus, a need exists to provide an improved technique to reduce the migration of metal atoms in integrated circuits to improve reliability. In addition, a need exists to provide the technique to reduce mechanical stress migration preferably without having to add extra steps to the manufacturing process.